1. Field of the Invention
The present invention relates in general to a synchronous dynamic random access memory (referred to hereinafter as SDRAM), and more particularly to a column address strobe (referred to hereinafter as CAS) signal generator for an SDRAM with at least two banks, which is capable of solving discordance between bank select addresses when a row address strobe (referred to hereinafter as RAS) signal and a CAS signal are generated in a test mode operation of the SDRAM.
2. Description of the Prior Art
Generally, an automatic refresh operation of an SDRAM is the same as a CAS-before-RAS (CBR) refresh operation of a DRAM. The automatic refresh operation is to input a row address from a refresh counter in the chip and advance a refresh cycle in response to the input row address.
The automatic refresh operation of the SDRAM has the following characteristics.
The automatic refresh operation is a self-timed RAS signal manner in which a RAS signal of a bank corresponding to a bank select address BS is driven after an automatic refresh command Auto Ref is applied, and then automatically returned to a precharge state after the lapse of a predetermined delay time. An automatic refresh exit command is not necessary.
The bank select address BS which is a least significant bit LSB of a refresh counter is toggled in each automatic refresh cycle (for example, in the case where the refresh counter provides its output signals up to All (bank select address BS) when a 16 M SDRAM has a 4 k cycle).
For a better understanding of the specification, the meaning of signals related to a general SDRAM will hereinafter be described.
The "CLK" signifies a system clock pin. In the SDRAM, all command operations are advanced synchronously with a system clock.
The "Bank" signifies each of the memory areas with different address fields. The banks have individually operable peripheral circuits, respectively. One bank performs a command, while simultaneously other banks selectively perform different commands.
The "command" signifies a command signal determined by the combination of signals /CS, /RAS, /CAS and /We.
The "Auto Refresh" signifies an automatic refresh command signal analogous to a CAS-before-RAS refresh in a conventional DRAM.
The "xcnt[0:n]" signifies output signals from the refresh counter corresponding to row addresses of 0 to n.
The "xcnt[BS]" signifies an output signal from the refresh counter corresponding to the bank select address BS. In the SDRAM, the signal xcnt[BS] corresponds to a least significant bit LSB of the refresh counter.
The "xcntine" signifies a sequentially increased signal from the refresh counter. The signal xcntine is generated in each automatic refresh cycle.
The "RAS.sub.-- Bk[0:1]" signifies a RAS signal corresponding to a bank 0 or bank 1. Namely, the RAS signal RAS.sub.-- Bk[0:1] controls both bank 0 and bank 1 in the 16 M SDRAM with the two banks. Similar to an output signal from a conventional row address strobe bar (/RAS) input buffer, the RAS signal RAS.sub.-- Bk[0:1] starts a row cycle, drives a selected word line and enables a bit line sensing operation.
The "MRS" signifies a mode register set command signal. In other words, the signal MRS means a cycle for programming the status of a mode register required in the SDRAM.
The "test mode" is an OP-code corresponding to a seventh bit of the mode register. If the OP-code is set to "H", the present mode is set to a test mode to enter a refresh counter test cycle.
The "WT" or "RD" signifies a burst write or read command signal. A burst mode is advanced by the number of clocks corresponding to a burst length programmed in the mode register.
The "Bk[i], [j]" indicates the status of one of a plurality of banks.
The "tRCD" signifies the time required from a RAS signal active point to a burst command point.
The "tRP" signifies a minimum RAS signal precharge time.
The "PCG.sub.-- All (precharge all banks)" signifies a signal for allowing all banks in the SDRAM to enter a precharge state at the same time.
The "tRRD" signifies the minimum time required from a RAS signal active point to the subsequent RAS signal active point, namely, a RAS signal active time difference between the successive banks.
The "BS" signifies an external bank select address input signal ("ADDRESS[BS]" in the drawing).
The "YA" signifies a column address where the burst mode is advanced. It is common that the column address YA is fixed to a desired value in the general test mode.
The automatic refresh and test mode operations of the conventional SDRAM will hereinafter be described with reference to FIGS. 1 to 4.
FIG. 1 is a block diagram illustrating the construction of a conventional refresh counter for an SDRAM. As shown in this drawing, the refresh counter includes a first counter circuit 11 for generating a bank select address signal xcnt [BS] of a least significant bit in response to an address signal xcntinc which is generated in each automatic refresh cycle. The bank select address signal xcnt[BS] is toggled in each automatic refresh cycle. The refresh counter further includes n counter circuits connected in series to the first counter circuit 11, for generating address signals corresponding to row addresses.
FIGS. 2a to 2g are timing diagrams illustrating an automatic refresh operation of the conventional refresh counter in FIG. 1 based on an automatic refresh command signal. The automatic refresh command signal is generated as shown in FIG. 2b by the combination of a chip select signal /CS, a row address strobe bar signal /RAS, a column address strobe bar signal /CAS and a write enable signal /We. Upon receiving the automatic refresh command signal, the first counter circuit 11 in the refresh counter in FIG. 1 generates the bank select address signal xcnt[BS] which is toggled in each automatic refresh cycle, as shown in FIG. 2d. A RAS signal RAS.sub.-- Bk1 corresponding to a bank 1 goes from low to high in logic, as shown in FIG. 2f, in response to the first automatic refresh command signal. The RAS signal RAS.sub.-- Bk1 remains at a high logic state for a predetermined time period. Then, a RAS signal RAS.sub.-- Bk0 corresponding to a bank 0 goes from low to high in logic, as shown in FIG. 2g, in response to the second automatic refresh command signal. The RAS signal RAS.sub.-- Bk0 remains at a high logic state for a predetermined time period.
FIG. 3A is a view illustrating the construction of a conventional RAS signal generator for the SDRAM. The RAS signal generator is adapted to generate RAS signals RAS.sub.-- BK[i] and RAS.sub.-- BK[j] for adjusting a row cycle. To this end, the RAS signal generator includes a RAS.sub.-- active input stage for allowing the RAS signal to enter an active state, a RAS precharge input stage for allowing the RAS signal to enter a precharge state, and a BS input stage being driven upon inputting a specified bank select address.
The RAS.sub.-- active input stage is driven in response to a command signal ROW.sub.-- active or an automatic refresh command signal to allow the RAS signal to rise from low to high in logic.
The RAS.sub.-- precharge input stage is driven in response to a precharge command signal or a self-timed delay signal to allow the RAS signal to fall from high to low in logic. However, in the test mode, the RAS precharge input stage is driven in response to the precharge command signal even in the automatic refresh command cycle to allow the RAS signal to go from high to low in logic. The self-timed delay signal is automatically generated in the chip after a bit line sensing operation is completed in the refresh cycle.
The BS input stage inputs an external bank select address signal ADDRESS[BS] in the normal state where the operation is performed in response to the command signal ROW.sub.-- active. Also, the BS input stage inputs the bank select address signal xcnt[BS] from the refresh counter in the automatic refresh command mode (or the test mode).
Further, the BS input stage is driven upon inputting a specified bank select address. As a result, even in the case where the RAS.sub.-- precharge input stage is driven, the RAS signal generator is suppressed in operation if the input signal is not a specified bank select address.
FIG. 3B is a view illustrating the construction of a conventional CAS signal generator for the SDRAM. The CAS signal generator is adapted to generate CAS signals CAS.sub.-- BK[i] and CAS.sub.-- BK[j] for adjusting a write or read column cycle. To this end, the CAS signal generator includes a CAS.sub.-- active input stage for allowing the CAS signal to enter an active state, a CAS.sub.-- precharge input stage for allowing the CAS signal to enter a precharge state, and a BS input stage being driven upon inputting a specified bank select address.
The CAS.sub.-- active input stage is driven in response to a burst write command signal or a burst read command signal to allow the CAS signal to go from low to high in logic.
The CAS.sub.-- precharge input stage is driven in response to a burst length end signal or a burst stop signal to allow the CAS signal to go from high to low in logic. The burst length end signal is automatically generated when the present burst length satisfies a burst length of a specified burst command. The burst stop signal is generated in the middle of the burst command operation.
The BS input stage is adapted to input a specified bank select address. As a result, even in the case where the CAS.sub.-- active or CAS.sub.-- precharge input stage is driven, the CAS signal generator is suppressed in operation if the input signal is not a specified bank select address.
FIGS. 4a to 4i are timing diagrams illustrating a test mode cycle operation of the conventional refresh counter in FIG. 1 based on the output signals from the conventional RAS and CAS signal generators in FIGS. 3A and 3B. The refresh counter enters the test mode in response to a mode register set command signal and the associated OP-code (test mode select bit). At this time, the self-timed RAS function is blocked differently from the normal automatic refresh operation. As a result, the RAS signal is returned to the precharge state in response to an external precharge command (herein, PCG.sub.-- All for allowing all the banks in the SDRAM to enter the precharge state at the same time) after the burst write or read cycle is advanced.
Noticeably, in contrast to the DRAM, the SDRAM must input the bank select address BS for selecting the corresponding one of multiple banks in the chip in the burst command mode corresponding to the column cycle. To this end, conventionally, the external bank select address signal ADDRESS[BS] is applied to the BS input stage of the CAS signal generator.
However, the bank select address signal xcnt[BS] from the internal refresh counter is supplied to the BS input stage in the automatic refresh command mode (for addressing, for example, the bank Bank [i]), and the CAS signal corresponding to the external bank select address signal ADDRESS[BS] is made active in the burst command mode (for addressing, for example, the bank Bank[j]) For this reason, if the bank select address signals xcnt [BS] and ADDRESS [BS] are different from each other, a desired burst write or read operation cannot be performed.